1. Field of the Invention
The present invention relates to a semiconductor device particularly including a circuit for redundancy such as a fuse.
2. Description of the Related Art
FIG. 5 is a block diagram of a semiconductor device 501 described in the following Patent Document 1. Macros 511 to 514 are each composed of normal blocks and a redundant block. The normal block is composed of a cell array. The redundant block is composed of the same cell array as that of the normal block, and when a defect occurs in any of the normal blocks, the redundant block operates as a replacement for this block. A fuse 502 designates a normal block to be replaced with the redundant block. A fuse 503 designates a macro to be connected to the fuse 502. A selection circuit 504 selectively connects any of the macros 511 to 514 and the fuse 502 according to the state of the fuse 503.
[Patent Document 1] Japanese Patent Application Laid-open No. 2004-39680
The number of connection wirings 515 between the selection circuit 504 and the macros 511 to 514 is large. The connection wirings 515 interfere with normal signal wirings. If the macros 511 to 514 are tested simultaneously, problems such as noise and voltage drop occur due to the simultaneous operation.